The present invention relates to semiconductor integrated circuits and, more particularly, to a circuit for measuring the phase margin of a delay-locked loop.
Delay-locked loops (DLLs) are used in integrated circuits for removing phase differences between clocks, such as phase differences caused by propagation delay. A typical DLL includes a phase/frequency detector, a charge pump, a loop capacitor and a voltage-controlled delay line. The phase/frequency detector detects a phase difference between a reference clock signal and a feedback clock signal. The phase/frequency detector generates a phase control signal as a function of the phase difference and applies the phase control signal to the charge pump, which increases or decreases a voltage across the loop capacitor. This voltage is applied to a control input of the voltage-controlled delay line for controlling the propagation delay through the delay line. The reference clock is passed through the delay line to generate a delayed DLL output clock, which is fed back to the phase detector as the feedback clock. The delay line advances or retards the phase of the DLL output clock until the phase of the feedback clock matches the phase of the reference clock. The DLL has then locked the DLL output clock signal onto the phase of the reference clock signal.
In integrated circuit applications, it is important that the phase margin of a DLL lies within predefined specifications. However, the phase margin can vary by as much as a factor of two or more from one integrated circuit to the next due to variations in process, supply voltage and temperature, which are known as “PVT”. Variations in the phase margin that exceed specified margins can lead to difficulties in clock synchronization and other functions commonly performed by DLLs. Therefore, it is desired to have the capability of measuring the phase margin for each integrated circuit instance and to use this measurement as part of a built-in self-test function for the DLL portion of the integrated circuit.